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Xcell Journal

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Xilinx Xcell Journal Article:

Using Xilinx FPGAs to Accelerate Packet Processing

by Andy Norton, Distinguished Engineer, Office of the CTO

Virtex devices enable the programmable FAST processors to decode, inspect and modify packets with minimal CPU involvement.


Next-generation network infrastructures are emerging as 10-Gigabit Ethernet matures and the industry looks ahead to 40 GbE and 100GbE...


Xilinx Xcell Journal Article:
Blade Management Controller Rides FPGA Embedded Processor

by Andy Norton, Distinguished Engineer, Office of the CTO, Jeff Mullins and Dick Mincher

Cloudshield builds powerful, flexible solution around Xilinx PowerPC 440 running embedded Linux.

The trend toward converged networks for both telecom and enterprise simplifies network infrastructure and dramatically lowers costs for companies and customers alike, providing them with scalable, open platforms to add new applications to their networks; thus extending the overall life and value of their networks. Today, blade platforms using Ethernet scaling from 1G/10G to 40G/100G play a key role in helping the industry achieving network convergence. But at the heart of this convergence are blade-management controllers that use standards-based Intelligent Platform Management Interfaces (IPMI).



Xilinx Xcell Journal Article:
Integrating EDK-Created Embedded Processor Subsystems

article link to PDF

by Andy Norton, President, Comm Logic Design, Inc.

Use Synplify Pro as the primary synthesis tool for complex designs containing embedded processors.

"The availability of embedded processor subsystems in FPGAs opens the door to a myriad of applications, including embedded network processors, flexible sandbox prototyping, control plane and data path subsystems, and exception handling processors. Today’s FPGAs integrate existing IP cores, interfaces, custom processing engines, and now embedded processor subsystems. You can easily instantiate these subsystems into a top-level HDL design just as you would integrate off-the-shelf IP...."



Application Note & Reference Design:

Synplify Design Flow using Xilinx EDK and Embedded Processor Subsystems

by Andy Norton, Comm Logic Design, Inc.

This application note describes the design flow when using the Synplicity Synthesis tools along with the Xilinx ISE and EDK (Embedded Design Kit) tools to build an Embedded Processor in a Xilinx FPGA.  Both the short version (as seen in Synplicity's Fall 2004 Syndicated news letter) and the full version (20 pages) of the application note are available by clicking on the appropriate button below.  In addition to the app note, a reference design is available for download as well.

"The availability of embedded processor subsystems in FPGAs opens the door to a myriad of applications including control plane subsystems, data path assist subsystems, exception handling processors, diagnostic and test subsystems capable of generating and analyzing data flows, manufacturing diagnostics and error testing...."

Short AppNote  Short Version of App Note (3 pages)

Full AppNote  Full Version of App Note (20 pages)

Ref Design  Download Reference Design (7MB *.zip)

Reference Design Install Notes:

Unzip the Reference Design in the c:\data\ 

The full unzipped project will be in c:\data\edktest\

The EDK subsystem is in c:\data\edktest\ppc_subsystem

The OS used was Windows XP Pro


Case Study:
IDT* PAX.port* 2500 content inspection engine (CIE) and Intel® IXP2400 network processor

(New Ways to Alleviate the Content Inspection Bottleneck in Security Systems)

by Intel

This Case Study cites "Proof of Concept Test Results" on page 3.  Comm Logic Design developed, performed and provided statistical analysis for these tests on behalf of our client IDT.  To read the full study, click the "Read More" button below.

"Can “off-the-shelf” processors achieve better throughput than custom-built ASICs in intrusion detection / prevention systems?  That’s the question posed by IDT in its mission to accelerate packet processing...."

Read More


EE Times Article:
NPUs and FPGAs: on different planes?

by Loring Wirbel of EE Times on July 26, 2004

This article discusses how NPUs (Network Processors) and FPGAs are increasingly found working together in networking products.  At Comm Logic Design we have many years of expertise melding NPUs and FPGAs in order to achieve optimal system solutions meeting performance and time-to-market objectives.

"One fringe benefit of all intelligence moving to the edge of the public network is that small boxes have to grapple with complex, multi-protocol tasks.... In either event, there are a lot of pretty complex chip sets inside those pizza boxes...."

Read More


EE Times Article:
Small system preps for deep-packet  inspection

by Loring Wirbel of EE Times on August 9, 2004

This article previews the CloudShield CA2000 deep-packet inspection system.  Comm Logic Design architected and developed the Silicon Database FPGA discussed in the article, and designed a significant amount of the Microcode used by the network processors.

"Colorado Springs, Colo. - Among the host of vendors claiming silicon support for deep-packet inspection, CloudShield Technologies Inc. claims it has taken acceleration of high-layer services to a new level by placing all control processing directly in the data plane.  Its Open Network Services Platform (ONSP), expanded this summer to include a modular 2RU chassis, integrates services through a silicon database that combines network processor and FPGA capabilities...."

Read More

Trademarks and logos used with permission of their respective holders.
IDT / Intel case study used with permission of Intel Corp. and IDT Corp.
EE Times Articles used with permission of Loring Wirbel of EE Times.


Last changed: 04/25/2012 17:45:16 Copyright © 2003 through 2012 Comm Logic Design, Inc.